1. Field of the Invention
The present invention relates, generally, to a memory system having data contents which are protected via an EDC method and, more particularly, to such a memory system wherein, in order to also recognize addressing errors, addresses are involved in the EDC coding.
2. Description of the Prior Art
The data contents of memory systems are often protected in such a way that a plurality of redundant bits are additionally co-stored under the address of a data word. These bits are called check bits, K-bits or ECC-bits and then arise by forming the parity sum over specific parts of the data word, which is usually referred to as EDC coding (xe2x80x9cEDCxe2x80x9d abbreviated for Error Detection Code). Upon readout of the memory word, the sub-parities are formed anew and compared to the allocated K-bits that are likewise readout. When there is equality for all K-bits, then it is concluded that the readout data word is error free. Given inequality, conclusions about the kind of error are drawn from the pattern of the non-coincidence, what is referred to as the syndrome pattern.
Those K-bit positions that do not agree in the above-described comparison are called syndromes. Specific syndrome patterns are decoded and the falsified bit position in the data word is thus potentially determined and corrected by inverting.
The formation of the K-bits (EDC encoding), the comparison of the K-bits, the decoding of the syndromes as well as the correction and potential alarm to a higher-ranking controller typically occurs with the assistance of specific controller modules, which are also referred to as EDC controllers below.
The document U.S. Pat. No. 5,164,944 discloses a memory system of this species.
When an addressing error is present, such error cannot be recognized by the previously described error monitoring system upon readout since the addressing error does not negatively affect the consistency of the data word. In order to also recognize addressing errors, it is not only the data word but also the memory address of the data word that is involved in the EDC encoding (i.e., in the parity formation) in a development of the error monitoring system.
As a result of involving the address in the EDC encoding, however, the outlay for the error monitoring system is considerably increased since, for example, twice the number of EDC controllers is required. Further, the EDC coding for data and address must be different.
Accordingly, in an embodiment of the present invention, a memory system is described wherein a check word is co-stored together with a respective data word, and wherein the memory system further includes: an error monitoring system, wherein the error monitoring system generates the check word, before the check word is co-stored, based on a data word to be written in and from a write address according to an EDC code formation rule, and wherein the error monitoring system generates the check word anew based on a data word to be read out from the memory system, and compares bits of the check word to bits stored for the data word and, given inequality, draws conclusions about a type of error from a syndrome pattern; and a time division multiplex means that enables generation, according to the same coding means, of the check word from the write address, and of the data word to be written in.
Additional features and advantages of the present invention are described in, and will be apparent from, the Detailed Description of the Preferred Embodiments and the Description of the Drawings.